The present invention relates to a clock signal generating device and, more particularly, to a clock signal generating device having a redundant configuration.
There has been extensively used a clock signal generating device capable of generating a clock signal for use in a utility apparatus in synchronism with a timing signal fed from the outside of the apparatus. This kind of device is disclosed in, e.g., Japanese Patent Laid-Open Publication No. 5-83238 (document 1) or No. 4-57536 (document 2). The devices taught in documents 1 and 2, however, have a problem that when an active and spare scheme is adopted, the system becomes sophisticated and expensive, as will be described specifically later.